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ispClock 5500 Family
TM
In-System Programmable Clock Generator with Universal Fan-Out Buffer
August 2004 Data Sheet
Features
10MHz to 320MHz Input/Output Operation Low Output to Output Skew (<50ps) Low Jitter Peak-to-Peak(<70ps) Up to 20 Programmable Fan-out Buffers
* Programmable output standards and individual enable controls - LVTTL, LVCMOS, HSTL, SSTL, LVDS, LVPECL * Programmable precision output impedance - 40 to 70 in 5 increments * Programmable slew rate * Up to 10 banks with individual VCCO and GND - 1.5V, 1.8V, 2.5V, 3.3V * Programmable lock detect * Multiply and divide ratio controlled by - Input divider (5 bits) - Internal feedback divider (5 bits) - Five output dividers (5 bits) * Programmable On-chip Loop Filter
Up to Five Clock Frequency Domains Flexible Clock Reference Inputs
* Programmable input standards - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL * Clock A/B selection multiplexer * Programmable precision termination
Four User-programmable Profiles Stored in E2CMOS(R) Memory
* Supports both test and multiple operating configurations
Fully Integrated High-Performance PLL
Full JTAG Boundary Scan Test In-System Programming Support Exceptional Power Supply Noise Immunity Commercial (0 to 70C) and Industrial (-40 to 85C) Temperature Ranges 100-pin and 48-pin TQFP Packages Applications
* Circuit board common clock generation and distribution * PLL-based frequency generation * High fan-out clock buffer
Precision Programmable Phase Adjustment (Skew) Per Output
* 16 settings; minimum step size 195ps - Locked to VCO frequency * Up to +/- 12ns skew range * Coarse and fine adjustment modes
Product Family Block Diagram
LOCK DETECT OUTPUT DIVIDERS BYPASS MUX * M FILTER VCO V3 V4 PLL CORE OUTPUT ROUTING MATRIX CLOCK OUTPUTS PHASE/ FREQUENCY DETECTOR N V2 V0 V1
SKEW CONTROL OUTPUT DRIVERS
REFERENCE INPUTS
JTAG INTERFACE & E2CMOS MEMORY
Multiple Profile Management Logic 0 1 2 3
INTERNAL FEEDBACK PATH
* Input Available only on ispClock 5520
(c) 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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clk5500_04
Lattice Semiconductor
ispClock5500 Family Data Sheet
General Description and Overview
The ispClock5510 and ispClock5520 are in-system-programmable high-fanout PLL-based clock drivers designed for use in high performance communications and computing applications. The ispClock5510 provides up to 10 single-ended or five differential clock outputs, while the ispClock5520 provides up to 20 single-ended or 10 differential clock outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVDS, LVPECL, LVTTL, LVCMOS, SSTL, HSTL) and output frequency. In addition, each output provides independent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-chip in nonvolatile E2CMOS memory. The ispClock5500's PLL and divider systems supports the synthesis of clock frequencies differing from that of the reference input through the provision of programmable input and feedback dividers. A set of five post-PLL V-dividers provides additional flexibility by supporting the generation of five separate output frequencies. Loop feedback may be taken from the output of any of the five V-dividers. The core functions of all members of the ispClock5500 family are identical, the differences between devices being restricted to the number of inputs and outputs, as shown in the following table. Table 1. ispClock5500 Family Members
Device ispClock5510 ispClock5520 Ref. Input Pairs 1 2 Clock Outputs 10 20
Figure 1. ispClock5510 Functional Block Diagram
PS0 PS1 LOCK RESET PLL_BYPASS SGATE GOE OEX OEY
Profile Select Control
OUTPUT ENABLE CONTROLS
0
1
2
3
LOCK DETECT OUTPUT DIVIDERS V0
(2-64)
OUTPUT ROUTING MATRIX
SKEW CONTROL
OUTPUT DRIVERS BANK_0A BANK_0B BANK_1A BANK_1B BANK_2A BANK_2B BANK_3A BANK_3B BANK_4A BANK_4B
INPUT DIVIDER REFA+ REFAREFVTT M
(1-32)
V1
(2-64)
1
PHASE DETECT
LOOP FILTER
V2
(2-64)
VCO
0
V3
(2-64)
N
(1-32)
FEEDBACK DIVIDER FEEDBACK SKEW ADJUST
V4
(2-64)
JTAG INTERFACE
TDI
TMS
TCK
TDO
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Lattice Semiconductor
Figure 2. ispClock5520 Functional Block Diagram
PS0 PS1 LOCK RESET PLL_BYPASS SGATE GOE OEX
ispClock5500 Family Data Sheet
OEY SKEW CONTROL OUTPUT DRIVERS BANK_0A BANK_0B BANK_1A
Profile Select Control
OUTPUT ROUTING MATRIX OUTPUT ENABLE CONTROLS
0
1
2
3
LOCK DETECT
BANK_1B BANK_2A BANK_2B OUTPUT DIVIDERS V0 BANK_3A BANK_3B BANK_4A
REFSEL REFA+ REFA0
(2-64)
INPUT DIVIDER M
(1-32)
1
V1
(2-64)
BANK_4B
REFVTT
1
REFB+ REFB-
PHASE DETECT
LOOP FILTER
V2
(2-64)
VCO
0
V3
(2-64)
SKEW CONTROL
OUTPUT DRIVERS BANK_5A BANK_5B
N
(1-32)
FEEDBACK DIVIDER
V4
(2-64)
BANK_6A BANK_6B BANK_7A BANK_7B BANK_8A BANK_8B BANK_9A JTAG INTERFACE FEEDBACK SKEW ADJUST BANK_9B
TDI
TMS
TCK
TDO
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Absolute Maximum Ratings
ispClock5500V Core Supply Voltage VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V PLL Supply Voltage VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V JTAG Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V Output Driver Supply Voltage VCCO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Output Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150C Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
ispClock5500V Symbol VCCD VCCJ VCCA VCCASLEW TJOP TA Parameter Core Supply Voltage JTAG I/O Supply Voltage Analog Supply Voltage VCCA Turn-on Ramp Rate Operating Junction Temperature Ambient Operating Temperature Commercial Industrial Commercial Industrial Conditions Min. 3.0 1.62 3.0 -- 0 -40 0 -40 Max. 3.6 3.6 3.6 0.033 100 115 701 851 Units V V V V/s C C
1. Device power dissipation may also limit maximum ambient operating temperature.
Recommended Operating Conditions - VCCO vs. Logic Standard
VCCO (V) Logic Standard LVTTL LVCMOS 1.8V LVCMOS 2.5V LVCMOS 3.3V SSTL2 Class 1 SSTL3 Class 1 HSTL Class 1 LVPECL (Differential) LVDS VCCO = 2.5V VCCO = 3.3V Min. 3.0 1.71 2.375 3.0 2.375 3.0 1.425 3.0V 2.375 3.0 Typ. 3.3 1.8 2.5 3.3 2.5 3.3 1.5 3.3V 2.5V 3.3 Max. 3.6 1.89 2.625 3.6 2.625 3.6 1.575 3.6V 2.625 3.6 Min. -- -- -- -- 1.15 1.30 0.68 -- -- -- VREF (V) Typ. -- -- -- -- 1.25 1.50 0.75 -- -- -- Max. -- -- -- -- 1.35 1.70 0.90 -- -- -- Min. -- -- -- -- VREF - 0.04 VREF - 0.05 -- -- -- -- VTT (V) Typ. -- -- -- -- -- VREF 0.5 x VCCO -- -- -- Max. -- -- -- -- VREF + 0.04 VREF + 0.05 -- -- -- --
Note: `--' denotes VREF or VTT not applicable to this logic standard
E2CMOS Memory Write/Erase Characteristics
Parameter Erase/Reprogram Cycles Conditions Min. 1000 Typ. -- Max. -- Units
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Performance Characteristics - Power Supply
Symbol ICCD ICCA ICCO Parameter Core Supply Current Analog Supply Current Output Driver Supply Current (per Bank) Conditions ispClock5510, fVCO = 640MHz ispClock5520, fVCO = 640MHz fVCO = 640MHz VCCO = 1.8V1, LVCMOS VCCO = 2.5V1, LVCMOS VCCO = 3.3V1, LVCMOS VCCO = 3.3V2, LVDS VCCJ = 1.8V VCCJ = 2.5V VCCJ = 3.3V Typ. 100 130 5.5 13 18 24 7.5 200 300 300 Max. 110 150 7 15 24 35 8 300 400 400 Units mA mA mA mA
ICCJ
JTAG I/O Supply Current (static)
A
1. Supply current consumed by each bank, both outputs active, 18pF load, 320MHz output frequency. 2. Supply current consumed by each bank, 100/5pF differential load, 320MHz output frequency.
DC Electrical Characteristics - Single-ended Logic
VIL (V) Logic Standard LVTTL/LVCMOS 3.3V LVCMOS 1.8V LVCMOS 2.5V SSTL2 Class 1 SSTL3 Class 1 HSTL Class 1 Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max. 0.8 0.35VCCO 0.7 VREF - 0.2 VREF - 0.1 Min. 2 0.65VCCO 1.7 VREF + 0.2 VREF + 0.1 VIH (V) Max. 3.6 3.6 3.6 3.6 3.6 3.6 VOL Max. (V) VOH Min. (V) 0.4 0.4 0.4 0.542 0.9 0.4
2 3
IOL (mA) 41 41 4
1
IOH (mA) -41 -41 -41 -7.6 -8 -8
VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.812 VCCO - 1.32 VCCO - 0.4
3
VREF - 0.18 VREF + 0.18
7.6 8 8
1. Specified for 50 internal series output termination. 2. Specified for 40 internal series output termination. 3. Specified for 20 internal series output termination.
DC Electrical Characteristics - LVDS
Symbol VICM VTHD VIN VOH VOL VOD VOD VOS VOS ISA ISAB Parameter Common Mode Input Voltage Differential Input Threshold Input Voltage Output High Voltage Output Low Voltage Output Voltage Differential Change in VOD between H and L Output Voltage Offset Change in VOS Between H and L Output Short Circuit Current Output Short Circuit Current VOD = 0V, Outputs Shorted to GND VOD = 0V, Outputs Shorted to Each Other Common Mode Output Voltage RT = 100 RT = 100 RT = 100 Conditions Min. 0.05 100 0 -- 0.9 250 -- 1.125 -- -- -- Typ. -- -- -- 1.375 1.03 400 -- 1.20 -- -- -- Max. 2.35 -- 2.4 1.60 -- 480 50 1.375 50 24 12 Units V mV V V V mV mV V mV mA mA
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Lattice Semiconductor
ispClock5500 Family Data Sheet
DC Electrical Characteristics - Differential LVPECL
Symbol VIH VIL VOH VOL Parameter Input Voltage High Input Voltage Low Output High Voltage1 Output Low Voltage1 Test Conditions VCCO = 3.0 to 3.6V VCCO = 3.3V VCCO = 3.0 to 3.6V VCCO = 3.3V VCCO = 3.0 to 3.6V VCCO = 3.3V VCCO = 3.0 to 3.6V VCCO = 3.3V Min. VCCO - 1.17 2.14 VCCO - 1.81 1.49 VCCO - 1.07 2.23 VCCO - 1.81 1.49 Typ. -- -- -- -- -- -- -- -- Max. VCCO - 0.88 2.42 VCCO - 1.48 1.83 VCCO - 0.88 2.42 VCCO - 1.62 1.68 Units V V V V
1. 100 differential termination.
DC Electrical Characteristics - Input/Output Loading
Symbol ILK IPU IPD IOLK
1. 2. 3. 4.
Parameter Input Leakage Input Pull-up Current Input Pull-down Current Tristate Leakage Output Note 1 Note 2 Note 3 Note 4
Conditions
Min. -- -- -- --
Typ. -- 80 120 --
Max. 10 120 150 10
Units A A A A
Applies to clock reference inputs when termination `open'. Applies to TDI, TMS inputs. Applies to REFSEL, PS0, PS1, GOE, SGATE and PLL_BYPASS. Applies to all logic types when in tristated mode.
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Switching Characteristics - Timing Adders for I/O Modes
Adder Type tIOI Input Adders2 LVTTL_in LVCMOS18_in LVCMOS25_in LVCMOS33_in SSTL2_in SSTL3_in HSTL_in LVDS_in LVPECL_in tIOO Output Adders1, 3 LVTTL_out LVCMOS18_out LVCMOS25_out LVCMOS33_out SSTL2_out SSTL3_out HSTL_out LVDS_out LVPECL_out tIOS Output Slew Rate Adders1 Slew_1 Slew_2 Slew_3 Slew_4 Output Slew_1 (Fastest) Output Slew_2 Output Slew_3 Output Slew_4 (Slowest) -- -- -- -- 0 330 660 1320 -- -- -- -- ps ps ps ps Output Configured as LVTTL Buffer Output Configured as LVCMOS 1.8V Buffer Output Configured as LVCMOS 2.5V Buffer Output Configured as LVCMOS 3.3V Buffer Output Configured as SSTL2 Buffer Output Configured as SSTL3 Buffer Output Configured as HSTL Buffer Output Configured as LVDS Buffer Output Configured as LVPECL Buffer -- -- -- -- -- -- -- -- -- 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns Using LVTTL Standard Using LVCMOS 1.8V Standard Using LVCMOS 2.5V Standard Using LVCMOS 3.3V Standard Using SSTL2 Standard Using SSTL3 Standard Using HSTL Standard Using LVDS Standard Using LVPECL Standard -- -- -- -- -- -- -- -- -- 0 0 0 0 0.4 0.4 0.4 1.8 1.8 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns Base Parameter(s) Description Min. Typ. Max. Units
1. Measured under standard output load conditions - see Figures 3-5. 2. All input adders referenced to LVTTL. 3. All output adders referenced to LVPECL.
Output Rise and Fall Times - Typical Values1, 2
Slew 1 (Fastest) Output Type LVTTL LVCMOS 1.8V LVCMOS 2.5V LVCMOS 3.3V SSTL2 SSTL3 HSTL LVDS
3
Slew 2 tR 0.85 1.05 0.90 0.85 0.85 0.80 0.85 -- -- tF 0.60 0.50 0.55 0.60 0.45 0.50 0.45 -- -- tR 1.20 1.40 1.20 1.20 1.45 1.45 1.30 -- --
Slew 3 tF 0.90 0.80 0.85 0.90 0.65 0.75 0.65 -- --
Slew 4 (Slowest) tR 1.75 2.00 1.80 1.75 2.30 2.30 1.90 -- -- tF 1.30 1.20 1.20 1.30 1.20 1.35 1.25 -- -- Units ns ns ns ns ns ns ns ns ns
tR 0.65 0.90 0.70 0.65 0.55 0.50 0.65 0.60 0.65
tF 0.45 0.40 0.40 0.45 0.35 0.40 0.35 0.60 0.60
LVPECL3
1. See Figures 3-5 for test conditions. 2. Measured between 20% and 80% points. 3. Only the `fastest' slew rate is available in LVDS and LVPECL modes.
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Output Test Loads
Figures 3-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and other selected parameters as noted in the various tables of this data sheet. Figure 3. CMOS Termination Load
Equivalent Termination Load Z=50 Test Point
50
1k
5pF
Figure 4. HSTL/SSTL Termination Load
Equivalent Termination Load 20 (HSTL) 40 (SSTL) Z=50 Test Point 5pF 50
VT=1.65 V (SSTL3) 1.25 V (SSTL2) 0.75 V (HSTL)
Figure 5. LVDS/LVPECL Termination Load
Equivalent Termination Load Z=50 +Test Point
Z=50
-Test Point
5pF
5pF
50
50
0.1F
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Programmable Input and Output Termination Characteristics
Symbol Parameter Conditions Rin=40 setting Rin=45 setting Rin=50 setting RIN Input Resistance Rin=55 setting Rin=60 setting Rin=65 setting Rin=70 setting CIN Input Capacitance Rout20 setting, VCCO=1.5V Rout20 setting, VCCO=1.8V Rout20 setting, VCCO=2.5V Rout20 setting, VCCO=3.3V Rout=40 setting ROUT Output Resistance Rout=45 setting Rout=50 setting Rout=55 setting Rout=60 setting Rout=65 setting Rout=70 setting Min. 38 42 48 51 55 60 62 -- -- -- -- -- 35 40 45 49 53 58 63 Typ. -- -- -- -- -- -- -- 7 27 22 20 18 -- -- -- -- -- -- -- Max. 42 46 53 57 62 68 73 -- -- -- -- -- 47 55 61 67 72 78 83 pF Units
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Performance Characteristics - PLL
Symbol fREF tCLOCKHI, tCLOCKLO tRINP, tFINP MDIV NDIV fPFD fVCO VDIV fOUT tJIT (cc) tJIT (per) DCERR tCO_BYPASS tL PSR
1. 2. 3. 4.
Parameter Reference input frequency range Reference input clock HIGH and LOW times Input rise and fall times M-divider range N-Divider range Phase detector input frequency range2 VCO operating frequency Output Divider range Output frequency range
1
Conditions
Min. 10 1.25
Typ. -- -- -- -- -- -- -- -- -- -- 55 11 -- -- 5 150 15 0.05
Max. 320 -- 5 32 32 320 640 64 320 160 70 14 260 300 -- 500 50 --
Units MHz ns ns
Measured between 20% and 80% levels
-- 1 1 10 320
MHz MHz
Even integer values only Fine Skew Mode, fVCO = 640MHz Coarse Skew Mode, fVCO = 640MHz 1000 cycle sample3 Note 3 Output type LVDS, VCCO = 3.3V5 Output type LVCMOS 3.3V fOUT < 100 MHz
5
2 10 5 -- -- -- -- -- -- -- --
MHz MHz ps (p-p) ps (RMS) ps ps ns s s ps(RMS) mV(p-p)
Output adjacent-cycle jitter Output period jitter Output duty cycle error (see Table 3 for nominal values)4
Reference clock to output delay, Inputs and Outputs configured to PLL bypass mode LVCMOS 3.3V standard PLL Lock time Power supply rejection, period jitter vs. power supply noise From Power-up event From Reset event fIN = fOUT = 100MHz VCCA = VCCD = VCCO modulated with 100kHz sinusoidal stimulus
In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design). Dividers should be set so that they provide the phase detector with signals of 10MHz or greater for loop stability. fIN = fOUT = 100 MHz, M = N = 1, V = 6, output type LVTTL, fastest slew rate, 50 output impedance. Variation in duty cycle expressed in ps. To obtain duty cycle percentage error (%ERR) for a given output frequency (fOUT), %ERR = 100 x fOUT x DCERR. 5. See Figures 3-5 for output loads.
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Timing Specifications
Skew Matching
Symbol tSKEW Parameter Output-output Skew Conditions Between any two identically configured and loaded outputs regardless of bank and output frequency Min. -- Typ. -- Max. 50 Units ps
Programmable Skew Control
Symbol Parameter Conditions Fine Skew Mode, fVCO = 320 MHz tSKRANGE Skew Control Range1 Fine Skew Mode, fVCO = 640 MHz Coarse Skew Mode, fVCO = 320 MHz Coarse Skew Mode, fVCO = 640 MHz SKSTEPS Skew Steps per range Fine Skew Mode, fVCO = 320 MHz tSKSTEP Skew Step Size2 Fine Skew Mode, fVCO = 640 MHz Coarse Skew Mode, fVCO = 320 MHz Coarse Skew Mode, fVCO = 640 MHz tSKERR Skew Time Accuracy3 Fine skew mode Coarse skew mode Min. -- -- -- -- -- -- -- -- -- -- -- Typ. 5.86 2.93 11.72 5.86 16 390 195 780 390 30 50 Max. -- -- -- -- -- -- -- -- -- -- -- ps ps ns Units
1. Skew control range is a function of VCO frequency (fVCO). In fine skew mode TSKRANGE = 15/(8 x fVCO). In coarse skew mode TSKRANGE = 15/(4 x fVCO). 2. Skew step size is a function of VCO frequency (fVCO). In fine skew mode TSKSTEP = 1/(8 x fVCO). In coarse skew mode TSKSTEP = 1/(4 x fVCO). 3. Only applicable to outputs with non-zero skew settings.
Control Functions
Symbol tDIS/OE tDIS/GOE tSUSGATE tPLL_RSTW tHPS_RST Parameter Delay Time, OEX or OEY to Output Disabled/ Enabled Delay Time, GOE to Output Disabled/Enabled Setup Time, SGATE to Output Clock Start/ Stop PLL Reset Pulse Width Hold time for RESET past change in PS[0..1] Conditions Min. -- -- 3 15 20 Typ. 10 10 -- -- -- Max. 20 20 -- -- -- Units ns ns cycles1 s ns
1. Output clock cycles for the particular output being controlled.
Figure 6. RESET and Profile Select Timing
PS[0..1] tHPS_RST RESET tPLL_RSTW
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Timing Specifications (Cont.)
Boundary Scan Logic
Symbol tBTCP tBTCH tBTCL tBTSU tBTH tBRF tBTCO tBTOZ tBTVO tBVTCPSU tBTCPH tBTUCO tBTUOZ tBTUOV Parameter TCK (BSCAN Test) Clock Cycle TCK (BSCAN Test) Pulse Width High TCK (BSCAN Test) Pulse Width Low TCK (BSCAN Test) Setup Time TCK (BSCAN Test) Hold Time TCK (BSCAN Test) Rise and Fall Rate TAP Controller Falling Edge of Clock to Valid Output TAP Controller Falling Edge of Clock to Data Output Disable TAP Controller Falling Edge of Clock to Data Output Enable BSCAN Test Capture Register Setup Time BSCAN Test Capture Register Hold Time BSCAN Test Update Register, Falling Edge of Clock to Valid Output BSCAN Test Update Register, Falling Edge of Clock to Output Disable BSCAN Test Update Register, Falling Edge of Clock to Output Enable Min. 40 20 20 8 10 50 -- -- -- 8 10 -- -- -- Max. -- -- -- -- -- -- 10 10 10 -- -- 25 25 25 Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns
JTAG Interface and Programming Mode
Symbol fMAX tCKH tCKL tISPEN tISPDIS tHVDIS tHVDIS tCEN tCDIS tSU1 tH tCO tPWV tPWP tBEW Parameter Maximum TCK Clock Frequency TCK Clock Pulse Width, High TCK Clock Pulse Width, Low Program Enable Delay Time Program Disable Delay Time High Voltage Discharge Time, Program High Voltage Discharge Time, Erase Falling Edge of TCK to TDO Active Falling Edge of TCK to TDO Disable Setup Time Hold Time Falling Edge of TCK to Valid Output Verify Pulse Width Programming Pulse Width Bulk Erase Pulse Width Condition Min. -- 20 20 15 30 30 200 -- -- 8 10 -- 30 10 200 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 25 -- -- -- -- -- -- 15 15 -- -- 15 -- -- -- Units MHz ns ns s s s s ns ns ns ns ns s ms ms
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Timing Diagrams
Figure 7. Erase (User Erase or Erase All) Timing Diagram
VIH
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tGKL
tH tBEW
tSU1
Clock to Shift-IR state and shift in the Discharge Instruction, then clock to the Run-Test/Idle state
tH tCKH
tSU1
tH tCKH
tSU1 tGKL
tH tCKH
tSU1
tH tCKH
TCK
VIL
tSU2
Specified by the Data Sheet
State
Update-IR
Run-Test/Idle (Erase)
The clock (TCK) must be able to run free with TMS = VIL
Select-DR Scan
Run-Test/Idle (Discharge)
The clock (TCK) must be able to run free with TMS = VIL
Figure 8. Programming Timing Diagram
VIH
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWP
tSU1
tH tCKH
Clock to Shift-IR state and shift in the next Instruction, which will stop the discharge process
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
TCK
VIL
State
Update-IR
Run-Test/Idle (Program)
The clock (TCK) must be able to run free with TMS = VIL
Select-DR Scan
Update-IR
Figure 9. Verify Timing Diagram
VIH
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWV
tSU1
tH tCKH
Clock to Shift-IR state and shift in the next Instruction
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
TCK
VIL
State
Update-IR
Run-Test/Idle (Program)
The clock (TCK) must be able to run free with TMS=VIL
Select-DR Scan
Update-IR
Figure 10. Discharge Timing Diagram
VIH
tHVDIS (Actual)
Clock to Shift-IR state and shift in the Verify Instruction, then clock to the Run-Test/Idle state
TMS
VIL
tSU1
VIH
tH tCKH
tSU1 tCKL
tH tPWP or tBEW
tSU1
tH tCKH
tSU1
tH tCKH
tSU1 tCKL
tH tCKH
tSU1 tPWV
Actual
tH tCKH
TCK
VIL
tPWV
Specified by the Data Sheet
State
Update-IR
Run-Test/Idle (Erase or Program)
Select-DR Scan
Run-Test/Idle (Verify)
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Typical Performance Characteristics
ICCD vs. fVCO (Normalized to 640MHz)
1.2 1.2
ICCO vs. Output Frequency (LVCMOS 3.3V, Normalized to 320MHz)
Normalized ICCO Current
1 0.8 0.6 0.4 0.2 0
Normalized ICCD Current
1 0.8 0.6 0.4 0.2 0 300
400
500
600
700
0
50
100
150
200
250
300
350
fVCO (MHz) Typical Skew Error vs. Setting (Skew Mode = FINE, fVCO = 600MHz)
Output Frequency (MHz)
100 75
Error vs. Ideal (ps)
50 25 0 -25 -50 -75
-100 0 3 6 9 12 15
Skew Setting #
Detailed Description
PLL Subsystem
The ispClock5500 provides an integrated phase-locked-loop (PLL) which may be used to generate output clock signals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the PLL are an edge-sensitive phase detector, a programmable loop filter, and a high-speed voltage-controlled oscillator (VCO). Additionally, a set of programmable input, output and feedback dividers (M, N, V[1..5]) is provided to support the synthesis of different output frequencies. Phase/Frequency Detector The ispClock5500 provides an edge-sensitive phase/frequency detector (PFD), which means that the device will function properly over a wide range of input clock reference duty cycles. It is only necessary that the input reference clock meet specified minimum HIGH and LOW times (tCLOCKHI, tCLOCKLO) for it to properly recognized by the PFD. The PFD's output is of a classical charge-pump type, outputting charge packets which are then integrated by the PLL`s loop filter. A lock-detection feature is also associated with the PFD. When the ispClock5500 is in a LOCKED state, the LOCK output pin goes LOW. The lock detector has two operating modes; phase lock mode and frequency lock mode. In phase-lock mode, the LOCK signal is asserted if the phases of the reference and feedback signals match, whereas in frequency-lock mode the LOCK signal is asserted when the frequencies of the feedback and reference signals
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Lattice Semiconductor
ispClock5500 Family Data Sheet
match. The option of which mode to use is programmable and may be set using PAC-Designer software (available from Lattice's web site at www.latticesemi.com). In phase-lock mode the lock detector asserts the LOCK signal as soon as a lock condition is determined. In frequency-lock mode, however, the PLL must be in a locked condition for a set number of phase detector cycles before the LOCK signal will be asserted. The number of cycles required before asserting the LOCK signal in frequency-lock mode can be set from 16 through 256, in increments of 16. When the lock condition is lost the LOCK signal will be de-asserted immediately both in phase and frequency-lock modes. Loop Filter A simplified schematic for the ispClock5500 loop filter is shown in Figure 11. The filter's capacitors are fixed, and the response is controlled by setting the value of the phase-detector's output current source's and the value of the variable resistor. The phase detector output current has 14 possible settings, ranging from 3A to 55A, while the resistor may be set to any one of six values ranging from 2.3K to 9.3K. This provides a total of 84 unique I-R combinations which may be selected. Figure 11. ispClock5500 Loop Filter (Simplified)
Phase Detector From M-divider I
To VCO I From N-divider C1 R C2
Because the selection of an optimal PLL loop filter can be a daunting task, PAC-Designer software offers a set of default filter settings which will provide acceptable performance for most applications. The primary criterion for selecting one of these settings is the total division factor used in the feedback path, or the ratio between the VCO output frequency and the frequency output by the N feedback divider (N x Vfeedback). Table 2 lists these default settings and conditions under which they should be used. Table 2. PAC-Designer Recommended Loop Filter Settings
N x VFBK 2 to 8 10 12 to 14 16 18 to 20 22 24 to 26 28 30 32 to 64 I (A) 5 7 9 11 13 15 17 19 21 22 R (k) 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3 2.3
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Lattice Semiconductor
ispClock5500 Family Data Sheet
The choice of loop filter parameters can have significant effects on settling time, output jitter, and whether the PLL will be fundamentally stable and be able to lock to an incoming signal. The values recommended in Table 2 were chosen to provide maximum loop stability while still providing exceptional jitter performance. Please note that when the skew mode is set to `coarse', the effective value of NxV must be doubled. Refer to the section titled `Coarse Skew Mode' on page 26 for more details. VCO The ispClock5500 provides an internal VCO which provides an output frequency ranging from 320MHz to 640MHz. The VCO is implemented using differential circuit design techniques which minimize the influence of power supply noise on measured output jitter. The VCO is also used to generate skews as a function of the total VCO period. Using the VCO as the basis for controlling output skew allows for highly precise and consistent skew generation, both from device-to-device, as well as channel-to-channel within the same device. M, N, and V Dividers The ispClock5500 incorporates a set of programmable dividers which provide the ability to synthesize output frequencies differing from that of the reference clock input. The input, or M, divider prescales the input reference frequency, and can be programmed with integer values over the range of 1 to 32. To achieve low levels of output jitter, it is best to use the smallest M divider value possible. The feedback, or N, divider prescales the feedback frequency and like the M divider, can also be programmed with integer values ranging from 1 to 32. Each one of the five output, or V, dividers can be independently programmed to provide even division ratios ranging from 2 to 64. When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (fk) may be calculated as: fk = fref N x Vfbk M x Vk (1)
where fk is the frequency of V divider k fref is the input reference frequency M and N are the input and feedback divider settings Vfbk is the setting of the V divider used to close the PLL feedback path Vk is the setting of the V divider used to provide output k Note that because the feedback may be taken from any V divider, Vk and Vfbk may refer to the same divider. Because the VCO has an operating frequency range spanning 320 MHz to 640 MHz, and the V dividers provide division ratios from 2 to 64, the ispClock5500 can generate output signals ranging from 5MHz to 320 MHz. For performance and stability reasons, however, there are several constraints which should be followed when selecting divider values: * Use the smallest feasible value for the M divider * The output frequency from the M (and N) divider should be greater or equal to 10 MHz. * The product of the N divider and the V divider used to close the PLL's feedback loop should be less than or equal to 64 (N x Vfbk 64) Output Duty Cycle The ispClock5500's output duty cycle varies as a function of the V divider used to generate that output. Table 3 shows the nominal output duty cycle as a function of the V divider setting. Note that if the output is inverted, the duty cycle will be equal to 100%-DC%, where DC% is the duty cycle indicated in the table. For example, with a Vdivider of 6, the non-inverted duty cycle from Table 3 will be 67%. For an inverted output, the duty cycle will be 100%-67% or 33%.
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Lattice Semiconductor
Table 3. Nominal Output Duty Cycle vs. V Divider Setting
V 2 4 6 8 10 12 14 16 DC% 50 50 67 50 40 50 43 50 V 18 20 22 24 26 28 30 32 DC% 44 50 45 50 46 50 47 50 V 34 36 38 40 42 44 46 48
ispClock5500 Family Data Sheet
DC% 47 50 47 50 48 50 48 50
V 50 52 54 56 58 60 62 64
DC% 48 50 48 50 48 50 48 50
PLL_BYPASS Mode The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the output of the M divider is routed directly to the inputs of the V dividers. In PLL_BYPASS mode, the nominal values of the V dividers are halved, so that they provide division ratios ranging from 1 to 32. The divide-by-1 setting, however, is invalid and will produce undefined results. The output frequency for a given V divider (fk) will be determined by fref (2) M x Vk Please note that PLL_BYPASS mode is provided primarily for testing purposes. When PLL_BYPASS mode is enabled, features such as lock detect and skew generation are unavailable. fk =
Reference Inputs
The ispClock5500 provides sets of configurable, internally-terminated inputs for clock reference signals. In normal operation, the clock reference input (REFA) is connected to the system clock from which the output signals are to be derived. The ispClock5510 provides one input signal pair for reference input, while the ispClock5520 provides two input pairs for reference signals. To select between reference inputs, the ispClock5520 provides a CMOS-compatible digital input called REFSEL. Table 4 shows the behavior of this control input: Table 4. REFSEL Operation for ispClock5520
REFSEL 0 1 Selected Input Pair REFA+/REFB+/-
Clock reference inputs may be configured to interface to signals from the following logic families with little or no external support circuitry: * * * * * * * LVTTL (3.3V) LVCMOS (1.8V, 2.5V, 3.3V) SSTL2 SSTL3 HSTL LVDS LVPECL (differential, 3.3V)
Each input also features internal programmable termination resistors, as shown in Figure 12.
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Figure 12. ispClock5500 Clock Reference Input Structure (REFA+/- Pair Shown)
ispClock5500 Single-ended Receiver REFA+ To Internal Logic
REFA-
Differential Receiver RT RT
REFVTT
The following usage guidelines are suggested for interfacing to supported logic families. LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V) The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the `+' terminal of the input pair (e.g. REFA+). The `-' input terminal should be left floating. CMOS transmission lines are generally source terminated, so all termination resistors should be set to the OPEN state. Figure 13 shows the proper configuration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a separate configuration setting for this particular standard. Figure 13. LVCMOS/LVTTL Input Receiver Configuration
ispClock5500 Signal In REFA+ Single-ended Receiver
No Connect REFART
OPEN No Connect REFVTT
HSTL, SSTL2, SSTL3 The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the `+' terminal of the input pair. The `-' input terminal should be tied to the appropriate Vref value, and the REFVTT terminal should be tied to a VTT termination supply. The positive input's terminating resistor should be engaged and set to 50. Figure 14 shows an appropriate configuration. Refer to the "Recommended Operating Conditions - Supported Logic Standards" table in this data sheet for suitable values of VREF and VTT. 18
Lattice Semiconductor
ispClock5500 Family Data Sheet
One important point to note is that the termination supplies must have low impedance and be able to both source and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage regulators, which can only source current. The best way to develop the necessary termination voltages is with a regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-performance memory busses, a suitable termination voltage supply is often already available in the system. Figure 14. SSTL2, SSTL3, HSTL Receiver Configuration
ispClock5500 Signal In REFA+ Differential Receiver
VREF IN REFA50
VTT CLOSED REFVTT OPEN
Differential HSTL and SSTL HSTL and SSTL are sometimes used in a differential form, especially for distributing clocks in high-speed memory systems. Figure 15 shows how ispClock5500 reference input should be configured for accepting these standards. The major difference between the differential and single-ended forms of these logic standards is that in the differential cases, the REFA- input is used as a signal input, not a reference level, and that both terminating resistors are engaged and set to 50. Figure 15. Differential HSTL/SSTL Receiver Configuration
ispClock5500 +Signal In REFA+ Differential Receiver
-Signal In REFA50 50
VTT CLOSED REFVTT CLOSED
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Lattice Semiconductor
ispClock5500 Family Data Sheet
LVDS/Differential LVPECL The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be engaged and set to 50. The REFVTT pin, however, should be left unconnected. This creates a floating 100 differential termination resistance across the input terminals. The LVDS termination configuration is shown in Figure 16. Figure 16. LVDS Input Receiver Configuration
ispClock5500
+Signal In LVDS Driver REFA+ -Signal In REFA50 50
Differential Receiver
CLOSED No Connect REFVTT
CLOSED
Note that while a floating 100 resistor forms a complete termination for an LVDS signal line, additional circuitry may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL output driver typically requires an external DC `pull-down' path to a VTERM termination voltage (typically VCC-2V) to properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5500's internal termination resistors should not be used for this pull-down function, as they may be damaged from excessive current. The pull-down should be implemented with external resistors placed close to the LVPECL driver (Figure 17) Figure 17. LVPECL Input Receiver Configuration
ispClock5500
+Signal In LVPECL Driver REFA+ -Signal In REFARPD RPD
Differential Receiver
50
50
CLOSED VTERM No Connect REFVTT
CLOSED
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Please note that while the above discussions specify using 50 termination impedances, the actual impedance required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The actual impedance required will be a function of the driver used to generate the signal and the transmission medium used (PCB traces, connectors and cabling). The ispClock5500's ability to adjust input impedance over a range of 40 to 70 allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to swap out components.
Output Drivers
The ispClock5500 provide banks of configurable, internally-terminated high-speed dual-output line drivers. The ispClock5510 provides five driver banks, while the ispClock5520 provides ten. Each of these driver banks may be configured to provide either a single differential output signal, or a pair of single-ended output signals. Programmable internal source-series termination allows the ispClock5500 to be matched to transmission lines with impedances ranging from 40 to 70 Ohms. The outputs may be independently enabled or disabled, either from E2CMOS configuration or by external control lines. Additionally, each can be independently programmed to provide a fixed amount of signal delay or skew, allowing the user to compensate for the effects of unequal PCB trace lengths or loading effects. Figure 18 shows a block diagram of a typical ispClock5500 output driver bank and associated skew control. Because of the high edge rates which can be generated by the ispClock5500's clock output drivers, the VCCO power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging from 0.01 to 0.1 F may be used for this purpose. Each bypass capacitor should be placed as close to its respective output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated parasitic inductances. In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground where possible. All GNDD pins must be tied to ground, regardless of whether or not the associated bank is used. Figure 18. ispClock5500 Output Driver and Skew Control
Skew Adjust From V-Dividers BANKxA
OE Control OE Control Single-ended `A' output Driver
Differential (PECL/LVDS) Driver
OE Control
Skew Adjust BANKxB
Single-ended `B' output Driver
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Each of the ispClock5500's output driver banks can be configured to support the following logic outputs: * * * * * * * LVTTL LVCMOS (1.8V, 2.5V, 3.3V) SSTL2 SSTL3 HSTL LVDS Differential LVPECL (3.3V)
To provide LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL outputs, the CMOS output drivers in each bank are enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of VCCO to be supplied to a given bank is determined by the logic standard to which that bank is configured. Because each pair of outputs has its own VCCO supply pin, each bank can be independently configured to support a different logic standard. Note that the two outputs associated with a bank must necessarily be configured to the same logic standard. The source impedance of each of the two outputs in each bank may be independently set over a range of 40 to 70 in 5 steps. A low impedance option (20) is also provided for cases where low source termination is desired on a given output, such as when using HSTL output mode. Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, and HSTL output modes. Four output slew-rate settings are provided, as specified in the "Output Rise Times" and "Output Fall Times" tables in this data sheet. To provide LVDS and differential LVPECL outputs, a separate driver is used which provides the correct LVDS or LVPECL logic levels when operating from a 3.3V VCCO. Because both LVDS and differential LVPECL transmission lines are normally terminated with a single 100 resistor between the `+' and `-' signal lines at the far end, the ispClock5500's internal termination resistors are not available in these modes. Also note that output slew-rate control is not available in LVDS or LVPECL mode, and that these drivers always operate at a fixed slew-rate. Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the polarity of each of the two output signals from each bank may be controlled independently. In the case of differential output standards, the polarity of the differential pair may be selected. Suggested Usage Figure 19 shows a typical configuration for the ispClock5500's output driver when configured to drive an LVTTL or LVCMOS load. The ispClock5500's output impedance should be set to match the characteristic impedance of the transmission line being driven. The far end of the transmission line should be left open, with no termination resistors. Figure 19. Configuration for LVTTL/LVCMOS Output Modes
ispClock5500
LVCMOS/LVTTL Mode Zo Ro = Zo LVCMOS/LVTTL Receiver
Figure 20 shows a typical configuration for the ispClock5500's output driver when configured to drive SSTL2, SSTL3, or HSTL loads. The ispClock5500's output impedance should be set to 40 for driving SSTL2 or SSTL3 22
Lattice Semiconductor
ispClock5500 Family Data Sheet
loads and to the 20 setting for driving HSTL. The far end of the transmission line must be terminated to an appropriate VTT voltage through a 50 resistor. Figure 20. Configuration for SSTL2, SSTL3, and HSTL Output Modes
ispClock5500 VTT
SSTL/HSTL Mode Zo=50 Ro : 40 (SSTL) 20 (HSTL)
RT=50 SSTL/HSTL Receiver
VREF
When driving differential SSTL or HSTL loads, the above configuration should be duplicated on the `-' output line of the differential pair. Figure 21 shows a typical configuration for the ispClock5500's output driver when configured to drive LVDS or differential LVPECL loads. The ispClock5500's output impedance is disengaged when the driver is set to LVDS or LVPECL mode. The far end of the transmission line must be terminated with a 100 resistor across the two signal lines. Figure 21. Configuration for LVDS and LVPECL Output Modes
LVDS/LVPECL mode Zo=50 RT=100 Zo=50 ispClock5500
LVDS/PECL Receiver
Note that when in LVPECL output mode, the ispClock5500's output driver provides an internal pull-down, unlike a typical bipolar LVPECL driver. For this reason no external pull-down resistors are necessary and the driver may be terminated with a single 100 resistor across the signal lines. For proper operation, pull-down resistors should NOT be used with the ispClock5500's LVPECL output mode.
Thermal Management
In applications where a majority of the ispClock5510 or ispClock5520's outputs are active and operating at or near maximum output frequency (320 MHz), package thermal limitations may need to be considered to ensure a successful design. Thermal characteristics of the packages employed by Lattice Semiconductor may be found in the document Thermal Management which may be obtained at www.latticesemi.com. The maximum current consumption of the digital and analog core circuitry is approximately 157mA worst case (ICCD + ICCA), and each of the output banks may draw up to 35mA worst case (LVCMOS 3.3V, CL=18pF, fOUT=320 MHz, both outputs in each bank enabled). This results in a total device dissipation: PDMAX = 3.3V x (10 x 35mA + 157mA) = 1.67W (3)
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Lattice Semiconductor
ispClock5500 Family Data Sheet
With a maximum recommended operating junction temperature (TJOP) of 115C for an industrial grade device, the maximum allowable ambient temperature (TAMAX) can be estimated as TAMAX = TJOP - PDMAX x JA = 115C - 1.67W x 35C/W = 56C where JA = 35 C/W in still air for the ispClock5520's TQFP100 package. The above analysis represents the worst-case scenario. Significant improvement in maximum ambient operating temperature can be realized with additional cooling. Providing a 200 LFM (Linear Feet per Minute) airflow reduces JA to 29C/W, which results in a maximum ambient operating temperature of 66C. In practice, however, the absolute worst-case situation will be relatively rare, as not all outputs may be running at maximum output frequency in a given application. Additionally, if the internal VCO is operating at less than its maximum frequency (640MHz), it requires less current on the VCCD pin. In these situations, one can estimate the effective ICCO for each bank and the effective ICCD for the digital core functions based on output frequency and VCO frequency. Normalized curves relating current to operating frequency for these parameters may be found in the Typical Performance Characteristics section. While it is possible to perform detailed calculations to estimate the maximum ambient operating temperature from operating conditions, some simpler rule-of-thumb guidance can also be obtained through the derating curves shown in Figure 22. The curves in Figure 22a show the maximum ambient operating temperature permitted when operating a given number of output banks at the maximum output frequency (320MHz). Note that it is assumed that both outputs in each bank are active. Figure 22. Maximum Ambient Temperature vs. Number of Active Output Banks
Temperature Derating Curves (Outputs LVCMOS 3.3V, fOUT=320 MHz)
90 Maximum Ambient Temp. C 80 70 60 50 40 0 2 4 6 8 10 90
(4)
Temperature Derating Curves (Outputs LVCMOS 3.3V, fOUT=100 MHz)
Maximum Ambient Temp. C
80 70 60 50 40 0 2 4 6 8 10
# Active Output Banks
# Active Output Banks
(a) Temperature Derating Curves (Outputs LVDS, fOUT=320 MHz)
5520 Commercial 5520 Industrial 5510 Commericial 5510 Industrial
(b)
Maximum Ambient Temp. C
90 80 70 60 50 40 0
2
4
6
8
10
# Active Output Banks
(c)
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Lattice Semiconductor
ispClock5500 Family Data Sheet
Figure 22b shows another derating curve, derived under the assumption that the output frequency is 100MHz. For many applications, 100MHz outputs will be a more realistic scenario. Comparing the maximum temperature limits of Figure 22b with Figure 22a, one can see that significantly higher operating temperatures are possible in LVCMOS 3.3V output mode with more outputs at 100MHz than at 320MHz. The examples above described examples using LVCMOS 3.3V logic, which represents the maximum power dissipation case at higher frequencies. For optimal operation at very high frequencies (> 150 MHz) LVDS will often be the best choice from a signal integrity standpoint. For LVDS-configured outputs, the maximum ICCO current consumption per bank is low enough that both the ispClock5510 and ispClock5520 can operate all outputs at maximum frequency over their complete rated temperature range, as shown in Figure 22c. Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced airflow present in a given design, actual die operating temperature is subject to considerable variation from that which may be theoretically predicted from package characteristics and device power dissipation.
Output Enable Controls
The ispClock5500 family provides the user with several options for enabling and disabling output pins, as well as suspending the output clock. In addition to providing the user with the ability to reduce the device's power consumption by turning off unused drivers, these features can also be used for functional testing purposes. The following inputs pins are used for output enable functions: * GOE - global output enable * OEX, OEY - secondary output enable controls * SGATE - synchronous output control Additionally, internal E2CMOS configuration bits are provided for the purpose of modifying the effects of these external control pins. When GOE is HIGH, all output drivers are forced into a high-Z state, regardless of any internal configuration. When GOE is LOW, the output drivers may also be enabled or disabled on an individual basis, and optionally controlled by the OEX and OEY pins. Internal E2CMOS configuration is used to establish whether the output driver is always enabled (when GOE pin is LOW), never enabled (permanently off), or selectively enabled by the state of either OEX or OEY. Bringing GOE high will also disable the internal feedback driver and will result in a loss of lock. Synchronous output gating is provided by ispClock5500 devices through the use of the SGATE pin. The SGATE pin does not disable the output driver, but merely forces the output to either a high or low state, depending on the output driver's polarity setting. If the output driver polarity is true, the output will be forced LOW when SGATE is brought LOW, while if it is inverted, the output will be forced HIGH. A primary feature of the SGATE function is that the clock output is enabled and disabled synchronous to the selected internal clock source. This prevents the generation of partial, `runt', output clock pulses, which would otherwise occur with simple combinatorial gating schemes. The SGATE is available to all clock outputs and is selectable on a pin-by-pin basis. Table 5 shows the behavior of the outputs for various combinations of the output enables, SGATE input, and E2CMOS configuration. Table 5. Clock Output Enable Functions
GOE X 0 0 0 0 0 1 OEX X X 0 1 X X X OEY X X X X 0 1 X E2 Configuration Always OFF Always ON Enable on OEX Enable on OEX Enable on OEY Enable on OEY n/a Output High-Z Clock Out Clock Out High-Z Clock Out High-Z High-Z
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Lattice Semiconductor
Table 6. SGATE Function
SGATE Bank Controlled by SGATE? X X 0 0 1 1 NO NO YES YES YES YES
ispClock5500 Family Data Sheet
Output Polarity True Inverted True Inverted True Inverted
Output Clock Inverted Clock LOW HIGH Clock Inverted Clock
Skew Control Units
Each of the ispClock5500's clock outputs is supported by a skew control unit which allows the user to insert an individually programmable delay into each output signal. This feature is useful when it is necessary to de-skew clock signals to compensate for physical length variations among different PCB clock paths. Unlike the skew adjustment features provided in many competing products, the ispClock5500's skew adjustment feature provides exact and repeatable delays which exhibit extremely low channel-to-channel and device-to-device variation. This is achieved by deriving all skew timing from the VCO, which results in the skew increment being a linear function of the VCO period. For this reason, skews are defined in terms of `time units' (TUs), which may be programmed by the user over a range of 0 to 15. The ispClock5500 family also supports both `fine' and `coarse' skew modes. In fine skew mode, the unit skew ranges from 195ps to 390 ps, while in the coarse skew mode unit skew varies from 390ps to 780ps. The value of one TU may be calculated from the VCO frequency (fvco) by using the following expressions: For fine skew mode, TU = 1 8fvco For coarse skew mode, TU = 1 4fvco (5)
When an output driver is programmed to support a differential output mode, a single skew setting is applied to both the BANKxA+ and BANKxB- signals. When the output driver is configured to support a single-ended output standard, each of the two single-ended outputs may be assigned independent skews. By using the internal feedback path, and programming a skew into the feedback skew control, it is possible to implement negative timing skews, in which the clock edge of interest appears at the ispClock5500's output before the corresponding edge is presented at the reference input. When the feedback skew unit is used in this way, the resulting negative skew is added to whatever skew is specified for each output. For example, if the feedback skew is set to 6TU, BANK1's skew is 8TU and BANK2's skew is 3TU, then BANK1's effective output skew will be 2TU (8TU-6TU), while BANK2's effective skew will be -3TU (3TU-6TU). This negative skew will manifest itself as BANK2's outputs appearing to lead the input reference clock, appearing as a negative propagation delay. Please note that the skew control units are only usable when the PLL is selected. In PLL bypass mode (PLL_BYPASS=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the device's propagation delay and the individual delays inherent in the output drivers consistent with the logic standard selected. Coarse Skew Mode The ispClock5500 family provides the user with the option of obtaining longer skew delays at the cost of reduced time resolution through the use of coarse skew mode. Coarse skew mode provides TU values ranging from 390ps (fVCO = 640MHz) to 780ps (fVCO = 320MHz), which is twice as long as those provided in fine skew mode. When coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the Vdivider bank, as shown in Figure 23. When assigning divider settings in coarse skew mode, one must account for this additional divide-by-two so that the VCO still operates within its specified range (320-640MHz).
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Lattice Semiconductor
Figure 23. Additional Factor-of-2 Division in Coarse Mode
Fine Mode
ispClock5500 Family Data Sheet
VCO
Coarse Mode
V-dividers
Fout
/2
When one moves from fine skew mode to coarse skew mode with a given divider configuration, the VCO frequency will attempt to double to compensate for the additional divide-by-2 stage. Because the fVCO range is not increased, however, one must modify the V-divider settings to bring fVCO back into its specified operating range (320MHz to 640MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will remain unchanged from what they were in fine mode. One drawback of moving from fine skew mode into coarse skew mode is that it may not be possible to maintain consistent output frequencies, as only those V-divider settings which are multiples of four (in fine mode) may be divided by two. For example, a V-divider setting of 24 will divide down to 12, which is also a legal V-divider setting, whereas an initial setting of 26 would divide down to 13, which is not a valid setting. When one moves from coarse skew mode to fine skew mode, the extra divide-by-two factor is removed from between the VCO and the V-divider bank, halving the VCO's effective operating frequency. To compensate for this change, all of the V-dividers must be doubled to move the VCO back into its specified operating range and maintain consistent output frequencies. The only situation in which this may be a problem is when a V-divider initially in coarse mode has a value greater than 32, as the corresponding fine skew mode setting would be greater than 64, which is not supported.
Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in the ispClock5500 family of devices. In the case where two outputs are identically configured, and driving identical loads, the maximum skew is defined by tSKEW, which is specified as a maximum of 50ps. In Figure 24 the Bank1A and BANK2A outputs show the skew error between two matched outputs. Figure 24. Skew Matching Error Sources
2ns +/- (tSKEW) +/- (tSKERR ) +/- t SKEW BANK1A (skew setting = 0) BANK2A (skew setting=0) BANK3A (skew setting = 2ns)
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Lattice Semiconductor
ispClock5500 Family Data Sheet
One can also program a user-defined skew between two outputs using the skew control units. Because the programmable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is very accurate. The typical error for any non-zero skew setting is given by the tSKERR specification. For example, if one is in fine skew mode with a VCO frequency of 500MHz, and selects a skew of 8TU, the realized skew will be 2ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the chart `Typical Skew Error vs. Setting' in the typical performance characteristics section. Note that this parameter adds to output-to-output skew error only if the two outputs have different skew settings. The Bank1A and Bank3A outputs in Figure 24 show how the various sources of skew error stack up in this case. Note that if two or more outputs are programmed to the same skew setting, then the contribution of the tSKERR skew error term does not apply. When outputs are configured or loaded differently, this also has an effect on skew matching. If an output is set to support a different logic type, this can be accounted for by using the tIOO output adders specified in the Table `Switching Characteristics'. That table specifies the additional skew added to an output using LVPECL as a baseline. For instance, if one output is specified as LVTTL (tIOO = 0.1ns), and another output is specified as LVPECL (tIOO = 0ns), then one could expect 0.1ns of additional skew between the two outputs. This timing relationship is shown in Figure 25a. Figure 25. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
660ps 0.1ns
LVPECL Output (TIOS = 0) LVTTL Output (TIOS = 0.1ns) (a)
LVCMOS Output (Slew rate=1) LVCMOS Output (Slew rate=3) (b)
Similarly, when one changes the slew rate of an output, the output slew rate adders (tIOS) can be used to predict the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are measured. For example, in the case of outputs configured to the same logic type (e.g. LVCMOS 1.8V), if one output is set to the fastest slew rate (1, tIOS = 0ps), and another set to slew rate 3 (tIOS = 660ps), then one could expect 660ps of skew between the two outputs, as shown in Figure 25b.
Other Features
Profile Select The ispClock5500 stores all internal configuration data in on-board E2CMOS memory. Up to four independent configuration profiles may be stored in each device. The choice of which configuration profile is to be active is specified thought the profile select inputs PS0 and PS1, as shown in Table 7. Table 7. Profile Select Function
PS1 0 0 1 1 PS0 0 1 0 1 Active Profile Profile 0 Profile 1 Profile 2 Profile 3
Each profile controls the following internal configuration items: * M divider setting * N divider setting * V divider settings 28
Lattice Semiconductor
* PLL Loop filter settings * Output Skew settings
ispClock5500 Family Data Sheet
Input/Output logic configuration (logic family, I/O impedance, slew rate) is independent of the profile selected. When a profile is changed by changing the values of the PS0 and PS1 inputs, it is necessary to assert a RESET signal to the ispClock5500 to restart the PLL and resynchronize all the internal dividers. RESET and Power-up Functions To ensure proper PLL startup and synchronization of outputs, the ispClock5500 provides both internally generated and user-controllable external reset signals. An internal reset is generated whenever the device is powered up. An external reset may be applied by asserting a logic HIGH at the RESET pin. Please note that the RESET pin does not have an internal pull-up or pull-down resistor associated with it and should be tied LOW if not used. Asserting RESET resets all internal dividers, and will cause the PLL to lose lock. On losing lock, the VCO frequency will begin dropping. The length of time required to regain lock is related to the length of time for which RESET was asserted. Output phase relationships among the outputs may not be valid until the ispClock5500 asserts its LOCK output. When the ispClock5500 begins operating from initial power-on, the VCO starts running at a very low frequency (<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being applied to the rest of the system, it is recommended that either the SGATE, OEX, or OEY pins be used to control the outputs based on the status of the LOCK pin. Holding the SGATE pin LOW during power-up will result in the BANK outputs being asserted HIGH or LOW (depending on inversion status) until SGATE is brought HIGH. Asserting OEX or OEY high will result in the BANK outputs being held in a high-impedance state until the OEX or OEY pin is pulled LOW. One should not use the GOE pin to control the outputs in anticipation of LOCK status, as holding GOE HIGH also disables internal feedback and will prevent the device from ever achieving lock.
Software-Based Design Environment
Designers can configure the ispClock5500 using Lattice's PAC-Designer software, an easy to use, Microsoft Windows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ispClock5500. A library of configurations is included with basic solutions and examples of advanced circuit techniques are available on the Lattice web site at www.latticesemi.com. In addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation. The PAC-Designer schematic window, shown in Figure 26 provides access to all configurable ispClock5500 elements via its graphical user interface. All analog input and output pins are represented. Static or non-configurable pins such as power, ground and the serial digital interface are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu commands. When completed, configurations can be saved and downloaded to devices. Figure 26. PAC-Designer Design Entry Screen (ispClock 5520)
29
Lattice Semiconductor In-System Programming
ispClock5500 Family Data Sheet
The ispClock5500 is an In-System Programmable (ISPTM) device. This is accomplished by integrating all E2CMOS configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispClock5500 instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E2CMOS memory of the ispClock5500. This consists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control data. The specifics this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security "fuse" (ESF) bit is provided in every ispClock5500 device to prevent unauthorized readout of the E2CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can not be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer software. Devices can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Included in the basic ispClock5500 Design Kit is an engineering prototype board that can be connected to the parallel port of a PC using a Lattice ispDOWNLOAD(R) cable. It demonstrates proper layout techniques for the ispClock5500 and can be used in real time to check circuit operation as part of the design process. Input and output connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5500 for a given application. (Figure 27).
Part Number PAC-SYSTEMCLK5520 PACCLK5520-EV Description Complete system kit, evaluation board, ispDOWNLOAD cable and software. Evaluation board only, with components, fully assembled.
Figure 27. Download from a PC
PAC-Designer Software
Other System Circuitry
ispDownload Cable (6') 4 ispClock5500 Device
30
Lattice Semiconductor
ispClock5500 Family Data Sheet
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5500 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ispClock5500 both as a serial programming interface, and for boundary scan test purposes. A brief description of the ispClock5500 JTAG interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ispClock5500. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct sequence, instructions are shifted into an instruction register which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing the configuration register, shifting data in, and then executing a program configuration instruction, after which the data is transferred to internal E2CMOS cells. It is these non-volatile cells that store the configuration or the ispClock5500. A set of instructions are defined that access all data registers and perform other internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 28 shows how the instruction and various data registers are organized in an ispClock5500. Figure 28. ispClock5500 TAP Registers
DATA REGISTER (90 BITS) E2CMOS NON-VOLATILE MEMORY
ADDRESS REGISTER (10 BITS)
UES REGISTER (32 BITS) MULTIPLEXER
IDCODE REGISTER (32 BITS)
B-SCAN REGISTER (56 BITS)
BYPASS REGISTER (1 BIT)
INSTRUCTION REGISTER (8 BITS)
TEST ACCESS PORT (TAP) LOGIC
OUTPUT LATCH
TDI
TCK
TMS
TDO
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as shown in Figure 29. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run31
Lattice Semiconductor
ispClock5500 Family Data Sheet
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state. Figure 29. TAP States
1 0 Test-Logic-Rst 0 Run-Test/Idle 1 1 Select-DR-Scan 0 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 0 1 Exit2-DR 1 Update-DR 1 0 1 0 0 0 1 1 1 Select-IR-Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 0 0 0 1 1
Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruction shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
32
Lattice Semiconductor
ispClock5500 Family Data Sheet
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ispClock5000 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and verified. For ispClock5000, the instruction word length is eight bits. All ispClock5000 instructions available to users are shown in Table 8. The following table lists the instructions supported by the ispClock5500 JTAG Test Access Port (TAP) controller: Table 8. ispClock5500 TAP Instruction Table
Instruction EXTEST ADDRESS_SHIFT DATA_SHIFT BULK_ERASE PROGRAM PROGRAM_SECURITY VERIFY DISCHARGE PROGRAM_ENABLE IDCODE USERCODE PROGRAM_USERCODE PROGRAM_DISABLE HIGHZ SAMPLE/PRELOAD CLAMP USER_LOGIC_RESET INTEST ERASE DONE PROG_INCR VERIFY_INCR PROGRAM_DONE NOOP BYPASS Code 0000 0000 0000 0001 0000 0010 0000 0011 0000 0111 0000 1001 0000 1010 0001 0100 0001 0101 0001 0110 0001 0111 0001 1010 0001 1110 0001 1000 0001 1100 0010 0000 0010 0010 0010 1100 0010 0100 0010 0111 0010 1010 0010 1111 0011 0000 1xxx xxxx External Test. Address register (10 bits) Address column data register (89 bits) Bulk Erase Program column data register to E2 Program Electronic Security Fuse Verify column Fast VPP Discharge Enable Program Mode Address Manufacturer ID code register (32 bits) Read UES data from E2 and addresses UES register (32 bits) Program UES register into E2 Disable Program Mode Force all outputs to High-Z state Capture current state of pins to boundary scan register Drive I/Os with boundary scan register Resets User Logic Performs in-circuit functional testing of device. Erases the `Done' bit only Program column data register to E2 and auto-increment address register Load column data register from E2 and auto-increment address register Programs the `Done' Bit Functions Similarly to CLAMP instruction Bypass - Connect TDO to TDI Description
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispClock5500. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The bit code for this instruction is defined by Lattice as shown in Table 8. The EXTEST (external test) instruction is required and will place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000). The optional IDCODE (identification code) instruction is incorporated in the ispClock5500 and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device
33
Lattice Semiconductor
ispClock5500 Family Data Sheet
type and version code (Figure 30). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 8. Figure 30. ispClock5500 Family ID Codes
MSB LSB
XXXX / 0000 0001 0101 0010 / 0000 0100 001 / 1
Version (4 bits) E2 Configured
Part Number (16 bits) 0152h = ispClock5510 (3.3V version)
JEDEC Manufacturer Identity Code for Lattice Semiconductor (11 bits)
Constant `1' (1 bit) per 1149.1-1990
MSB
LSB
XXXX / 0000 0001 0101 0000 / 0000 0100 001 / 1
Version (4 bits) E Configured
2
Part Number (16 bits) 0150h = ispClock5520 (3.3V version)
JEDEC Manufacturer Identity Code for Lattice Semiconductor (11 bits)
Constant `1' (1 bit) per 1149.1-1990
In addition to the four instructions described above, there are 20 unique instructions specified by Lattice for the ispClock5520. These instructions are primarily used to interface to the various user registers and the E2CMOS nonvolatile memory. Additional instructions are used to control or monitor other features of the device, including boundary scan operations. A brief description of each unique instruction is provided in detail below, and the bit codes are found in Table 8. PROGRAM_ENABLE - This instruction enables the ispClock5500's programming mode. PROGRAM_DISABLE - This instruction disables the ispClock5500's programming mode. BULK_ERASE - This instruction will erase all E2CMOS bits in the device, including those the UES data and electronic security fuse (ESF). A bulk erase instruction must be issued before reprogramming a device. The device must already be in programming mode for this instruction to execute. ADDRESS_SHIFT - This instruction shifts address data into the address register (10 bits) in preparation for either a PROGRAM or VERIFY instruction. DATA_SHIFT - This instruction shifts data into or out of the data register (90 bits), and is used with both the PROGRAM and VERIFY instructions. PROGRAM - This instruction programs the contents of the data register to the E2CMOS memory column pointed to by the address register. The device must already be in programming mode for this instruction to execute. PROG_INCR - This instruction first programs the contents of the data register into E2CMOS memory column pointed to by the address register and then auto-increments the value of the address register. The device must already be in programming mode for this instruction to execute. PROGRAM_SECURITY - This instruction programs the electronic security fuse (ESF). This prevents data other than the ID code and UES strings from being read fro the device. The electronic security fuse may only be reset by issuing a BULK_ERASE command. The device must already be in programming mode for this instruction to execute. 34
Lattice Semiconductor
ispClock5500 Family Data Sheet
VERIFY - This instruction loads data from the E2CMOS array into the column register. The data may then be shifted out. The device must already be in programming mode for this instruction to execute. VERIFY_INCR - This instruction copies the E2CMOS column pointed to by the address register into the data column register and then auto-increments the value of the address register. The device must already be in programming mode for this instruction to execute. DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or programming cycle and prepares ispClock5500 for a read cycle. PROGRAM_USERCODE - This instruction writes the contents of the UES register (32 bits) into E2CMOS memory. The device must already be in programming mode for this instruction to execute. USERCODE - This instruction both reads the UES string (32 bits) from E2CMOS memory into the UES register and addresses the UES register so that this data may be shifted in and out. HIGHZ - This instruction forces all outputs into a High-Z state. CLAMP - This instruction drives I/O pins with the contents of the boundary scan register. USER_LOGIC_RESET - This instruction resets all user-accessible logic, similar to asserting a HIGH on the RESET pin. INTEST - This instruction performs in-circuit functional testing of the device. ERASE_DONE - This instruction erases the `DONE' bit only. This instruction is used to disable normal operation of the device while in programming mode until a valid configuration pattern has been programmed. PROGRAM_DONE - This instruction programs the `DONE' bit only. This instruction is used to enable normal device operation after programming is complete. NOOP - This instruction behaves similarly to the CLAMP instruction.
35
Lattice Semiconductor
ispClock5500 Family Data Sheet
Pin Descriptions
Pin Number Pin Name VCCO_0 VCCO_1 VCCO_2 VCCO_3 VCCO_4 VCCO_5 VCCO_6 VCCO_7 VCCO_8 VCCO_9 GNDO_0 GNDO_1 GNDO_2 GNDO_3 GNDO_4 GNDO_5 GNDO_6 GNDO_7 GNDO_8 GNDO_9 BANK_0A BANK_0B BANK_1A BANK_1B BANK_2A BANK_2B BANK_3A BANK_3B BANK_4A BANK_4B BANK_5A BANK_5B BANK_6A BANK_6B BANK_7A BANK_7B BANK_8A BANK_8B BANK_9A BANK_9B VCCA GNDA Description Output Driver `0' VCC Output Driver `1' VCC Output Driver `2' VCC Output Driver `3' VCC Output Driver `4' VCC Output Driver `5' VCC Output Driver `6' VCC Output Driver `7' VCC Output Driver `8' VCC Output Driver `9' VCC Output Driver `0' Ground Output Driver `1' Ground Output Driver `2' Ground Output Driver `3' Ground Output Driver `4' Ground Output Driver `5' Ground Output Driver `6' Ground Output Driver `7' Ground Output Driver `8' Ground Output Driver `9' Ground Clock Output driver 0, `A' output Clock Output driver 0, `B' output Clock Output driver 1, `A' output Clock Output driver 1, `B' output Clock Output driver 2, `A' output Clock Output driver 2, `B' output Clock Output driver 3, `A' output Clock Output driver 3, `B' output Clock Output driver 4, `A' output Clock Output driver 4, `B' output Clock Output driver 5, `A' output Clock Output driver 5, `B' output Clock Output driver 6, `A' output Clock Output driver 6, `B' output Clock Output driver 7, `A' output Clock Output driver 7, `B' output Clock Output driver 8, `A' output Clock Output driver 8, `B' output Clock Output driver 9, `A' output Clock Output driver 9, `B' output Analog VCC for PLL circuitry Analog Ground for PLL circuitry Pin Type Power Power Power Power Power Power Power Power Power Power GND GND GND GND GND GND GND GND GND GND Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Power GND ispClock5510 48 TQFP 1 5 9 25 29 -- -- -- -- -- 4 8 12 28 32 -- -- -- -- -- 3 2 7 6 11 10 27 26 31 30 -- -- -- -- -- -- -- -- -- -- 13 14 ispClock5520 100 TQFP 3 7 11 15 19 51 55 59 63 67 6 10 14 18 22 54 58 62 66 70 5 4 9 8 13 12 17 16 21 20 53 52 57 56 61 60 65 64 69 68 30 31
36
Lattice Semiconductor
ispClock5500 Family Data Sheet
Pin Descriptions (Continued)
Pin Number Pin Name VCCD GNDD VCCJ REFA+ REFAREFB+ REFBREFSEL REFVTT TDO TDI TCK TMS LOCK SGATE GOE OEX OEY PS0 PS1 RESET TEST1 TEST2 n/c Reserved Description Digital Core VCC Digital GND JTAG interface VCC Clock Reference A positive input Clock Reference A negative input Clock Reference B positive input Clock Reference B negative input Clock Reference Select input (LVCMOS) Termination voltage for reference inputs JTAG TDO Output line JTAG TDI Input line JTAG Clock Input JTAG Mode Select PLL Lock indicator, LOW indicates PLL lock Synchronous output gate Global Output Enable Output Enable 1 Output Enable 2 Profile Select 0 Profile Select 1 Reset PLL Test Input 1 - connect to GNDD Test Input 2 - connect to GNDD No internal connection Factory use only - Do not connect Pin Type Power GND Power Input Input Input Input Input1 Power Output Input Input
2
ispClock5510 48 TQFP 24, 33 15, 16, 17, 23, 48 36 18 19 -- -- -- 20 35 39 38 37 34 40 42 21 22 44 43 47 41 46 45 -- --
ispClock5520 100 TQFP 47, 71 32, 33, 34, 35, 36, 37, 46, 93 74 38 39 42 41 43 40 73 84 83 82 72 85 87 44 45 89 88 92 86 91 90 1, 2, 23, 24, 25, 26, 27, 28, 29, 48, 49, 50, 75, 76, 77, 78, 79, 94, 97, 98, 99, 100 80, 81, 95, 96
Input
2
Output Input1 Input1 Input Input Input1 Input1 Input
1
PLL_BYPASS PLL Bypass
Input Input Input n/a n/a
1. Internal pull-down resistor. 2. Internal pull-up resistor.
Detailed Pin Descriptions
VCCO_[0..9], GNDO_[0..9] - These pins provide power and ground for each of the output banks. In the case when an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1uF as close to its VCCO and GNDO pins as is practical. BANK_[0..9]A, BANK_[0..9]B - These pins provide clock output signals. The choice of output divider (V0-V4) and output driver type (CMOS, LVDS, SSTL, etc.) may be selected on a bank-by-bank basis. When the outputs are configured as pairs of single-ended outputs, output impedance and slew rate may be selected on an output-by-output basis.
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Lattice Semiconductor
ispClock5500 Family Data Sheet
VCCA, GNDA - These pins provide analog supply and ground for the ispClock5500 family's internal analog circuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immunity, it is suggested that the supply to the VCCA pin be isolated from other circuitry with a ferrite bead. VCCD, GNDD - These pins provide digital supply and ground for the ispClock5500 family's internal digital circuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. to improve noise immunity it is suggested that the supply to the VCCD pins be isolated with ferrite beads. VCCJ - This pin provides power and a reference voltage for use by the JTAG interface circuitry. It may be set to allow the ispClock5500 family devices to function in JTAG chains operating at voltages differing from VCCD. REFA+, REFA-, REFB+, REFB- - These input pins provide the inputs for clock signals, and can accommodate either single ended or differential signal protocols by using either just the `+' pins, or both the `+' and `-` pins. Two sets of inputs are provided to accommodate the use of different signal sources and redundant clock sources. REFSEL - This input pin is used to select which clock input pair (REFA+/- or REB+/-) is selected for use as the reference input. When REFSEL=0, REFA+/- is used, and when REFSEL=1, REFB+/- is used. REFVTT - This pin is used to provide a termination voltage for the reference inputs when they are configured for SSTL or HSTL logic, and should be connected to a suitable voltage supply in those cases. TDO, TDI, TCK, TMS - These pins comprise the ispClock5500 device's JTAG interface. The signal levels for these pins are determined by the selection of the VCCJ voltage. LOCK - This output pin indicates that the device's PLL is in a locked condition when it goes low. SGATE - This input pin provides a synchronous gating function for the outputs, which may be enabled on a bankby-bank basis. When the synchronous gating function is enabled for a given bank, that bank's outputs will output a clock signal when the SGATE pin is HIGH, and will drive a constant HIGH or LOW when the SGATE pin is LOW. Synchronous gating ensures that when the state of SGATE is changed, no partial clock pulses will appear at the outputs. OEX, OEY - These pins are used to enable the outputs or put them into a high-impedance condition. Each output may be set so that it is always on, always off, enabled by OEX or enabled by OEY. GOE - Global output enable. This pin drives all outputs to a high-impedance state when it is pulled HIGH. GOE also controls the internal feedback buffer, so that bringing GOE high will cause the PLL to lose lock. PS0, PS1 - These input pins are used to select one of four user-defined configuration profiles for the device. PLL_BYPASS - When this pin is pulled LOW, the V-dividers are driven from the output of the device's VCO, and the device behaves as a phase-locked loop. When this pin is pulled HIGH, the V-dividers are driven directly from the output of the M-divider, and the PLL functions are effectively bypassed. RESET - When this pin is pulled HIGH, all on-board counters are reset, and lock is lost. TEST1,TEST2 - These pins are used for factory test functions, and should always be tied to ground. n/c - These pins have no internal connection. We recommend that they be left unconnected. RESERVED - These pins are reserved for factory use and should be left unconnected.
38
Lattice Semiconductor
ispClock5500 Family Data Sheet
Package Diagrams
48-Pin TQFP (Dimensions in Millimeters)
PIN 1 INDICATOR
0.20 C A-B D D
N
0.20 H A-B D
D1
3. A
1
E B e D 8. 4X 3.
E1
3.
SEE DETAIL "A" H b C SEATING PLANE A A2
B
GAUGE PLANE 0.25
0.08
M C A -B D 0.08 C LEAD FINISH b 1.00 REF. A1 0.20 MIN.
B
0-7 L
c
c1
b
DETAIL "A"
1 BASE METAL
SECTION B - B
SYMBOL MIN. 0.05 1.35 NOM. 1.40 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.45 0.60 48 0.50 BSC 0.17 0.17 0.09 0.09 0.22 0.20 0.15 0.13 0.27 0.23 0.20 0.16 0.75 MAX. 1.60 0.15 1.45
NOTES:
1. 2. 3. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1 DIMENSIONS.
A A1 A2 D D1 E E1 L N e b b1 c c1
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
7.
8.
39
Lattice Semiconductor 100-Pin TQFP (Dimensions in Millimeters)
PIN 1 INDICATOR
ispClock5500 Family Data Sheet
0.20 C A-B D
D 100X
e
8 TOP VIEW
0.20 M C A-B
c
NOTES:
1. 2. 3. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1 DIMENSIONS.
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
7.
8.
3 A E B 3 E1 D 3 4X SIDE VIEW SEE DETAIL 'A' 0.20 H A-B D D1 BOTTOM VIEW
b
D
SEATING PLANE
C H A A2
B
GAUGE PLANE 0.25
b
LEAD FINISH 0.10 C c1 A1 0.20 MIN.
B
0-7 L
b
DETAIL 'A' 1 BASE METAL
1.00 REF.
SECTION B-B
SYMBOL A A1 A2 D D1 E E1 L N e b b1 c c1
MIN. 0.05 1.35
NOM. 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC
MAX. 1.60 0.15 1.45
0.45
0.60 100 0.50 BSC
0.75
0.17 0.17 0.09 0.09
0.22 0.20 0.15 0.13
0.27 0.23 0.20 0.16
40
Lattice Semiconductor
ispClock5500 Family Data Sheet
Part Number Description
ispPAC-CLK55XX X - 01 XXXX X
Device Family Device Number CLK5510 CLK5520 Grade I = Industrial Temp. Range C = Commercial Temp. Range Package T48 = 48-pin TQFP T100 = 100-pin TQFP TN48 = Lead-Free 48-pin TQFP TN100 = Lead-Free100-pin TQFP Performance Grade 01 = Standard Operating Voltage V = 3.3V
Ordering Information
Conventional Packaging
Commercial
Part Number ISPPAC-CLK5510V-01T48C ispPAC-CLK5520V-01T100C Clock Outputs 10 20 Supply Voltage 3.3V 3.3V Package TQFP TQFP Pins 48 100
Industrial
Part Number ISPPAC-CLK5510V-01T48I ispPAC-CLK5520V-01T100I Clock Outputs 10 20 Supply Voltage 3.3V 3.3V Package TQFP TQFP Pins 48 100
Lead-Free Packaging
Commercial
Part Number ISPPAC-CLK5510V-01TN48C ispPAC-CLK5520V-01TN100C Clock Outputs 10 20 Supply Voltage 3.3V 3.3V Package Lead-Free TQFP Lead-Free TQFP Pins 48 100
Industrial
Part Number ISPPAC-CLK5510V-01TN48I ispPAC-CLK5520V-01TN100I Clock Outputs 10 20 Supply Voltage 3.3V 3.3V Package Lead-Free TQFP Lead-Free TQFP Pins 48 100
41
Lattice Semiconductor
ispClock5500 Family Data Sheet
Package Options
ispClock5510: 48-pin TQFP
PLL_BYPASS TEST1 TEST2 RESET SGATE TDI TCK 41 40 39 38 GNDD
PS0 PS1 GOE
48
47 46 45
44 43 42
37
TMS
VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34
VCCJ TDO LOCK VCCD GNDO_4 BANK_4A BANK_4B VCCO_4 GNDO_3 BANK_3A BANK_3B VCCO_3
ispPACCLK5510V-01T48C
33 32 31 30 29 28 27 26 25
13
14 15 16
17 18 19
20 21 22 23 REFVTT OEX OEY GNDD
GNDD REFA+ REFA-
GNDA GNDD GNDD
VCCA
42
VCCD
24
Lattice Semiconductor ispClock5520: 100-pin TQFP
GNDD PLL_BYPASS TEST1 TEST2 Reserved Reserved n/c
ispClock5500 Family Data Sheet
TCK TMS Reserved
Reserved n/c n/c 80 79 78
RESET SGATE TDI
PS0 PS1 GOE
n/c
n/c n/c n/c
100
99 98 97
96 95 94
93 92 91 90
89 88 87
86 85 84
83 82 81
n/c n/c VCCO_0 BANK_0B BANK_0A GNDO_0 VCCO_1 BANK_1B BANK_1A GNDO_1 VCCO_2 BANK_2B BANK_2A GNDO_2 VCCO_3 BANK_3B BANK_3A GNDO_3 VCCO_4 BANK_4B BANK_4A GNDO_4 n/c n/c n/c
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
n/c n/c
n/c VCCJ TDO LOCK VCCD GNDO_9 BANK_9A BANK_9B VCCO_9 GNDO_8 BANK_8A BANK_8B VCCO_8 GNDO_7 BANK_7A BANK_7B VCCO_7 GNDO_6 BANK_6A BANK_6B VCCO_6 GNDO_5 BANK_5A BANK_5B VCCO_5
ispPAC-CLK5520V-01T100C
26
27 28 29
30 31 32
33 34 35 36
37 38 39
40 41 42
43 44 45
46 47 48 GNDD VCCD n/c
VCCA GNDA GNDD
GNDD GNDD GNDD GNDD
GNDD REFA+ REFA-
n/c
n/c n/c n/c
REFVTT REFBREFB+
43
RFSEL OEX OEY
n/c n/c
49 50

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